From e61dd0f7a2be83ce5ba87d74f7384111576ffd49 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 6 May 2014 23:53:09 +1000 Subject: southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/supermicro/h8scm/romstage.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 0f5abdf30e..e7a1c4c834 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -31,8 +31,6 @@ #include "northbridge/amd/agesa/family10/reset_test.h" #include #include -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "superio/nuvoton/wpcm450/wpcm450.h" #include #include @@ -122,14 +120,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); -- cgit v1.2.3