From e166782f397f7db2c4446c5e120fa30afbde7bdd Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 5 May 2012 15:29:32 +0200 Subject: Clean up #ifs Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich Reviewed-by: Martin Roth --- src/mainboard/supermicro/h8dme/get_bus_conf.c | 4 ++-- src/mainboard/supermicro/h8dme/romstage.c | 4 ++-- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 4 ++-- src/mainboard/supermicro/h8dmr/romstage.c | 4 ++-- src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 4 ++-- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 6 +++--- src/mainboard/supermicro/h8qgi/mainboard.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.h | 4 ++-- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 2 +- src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c | 4 ++-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c | 4 ++-- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- 16 files changed, 26 insertions(+), 26 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 42c4c46e7f..53dcd7206d 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -24,7 +24,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include #endif @@ -141,7 +141,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 2cdc4c943e..989f2d8872 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -16,7 +16,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -217,7 +217,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 42c4c46e7f..53dcd7206d 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -24,7 +24,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include #endif @@ -141,7 +141,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 38aef5ea4f..cdef306dbc 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 07350e3f77..0cb580cd3d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include #endif @@ -115,7 +115,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 4e243c284e..ddd0920e77 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 5837349692..d73e8ad3b0 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -202,7 +202,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT == 1 +#if CONFIG_HT3_SUPPORT /** * The socket and link match values are platform specific * @@ -439,10 +439,10 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* -#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 675c87fa3b..f6d437eab2 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -72,7 +72,7 @@ static void h8qgi_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +#if CONFIG_HAVE_MAINBOARD_RESOURCES int add_mainboard_resources(struct lb_memory *mem) { return 0; diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h index 8f45019783..3ba25d5006 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -31,10 +31,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index aac61ec464..42cd3635a1 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -40,7 +40,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index f03fb64e81..a92bf424ae 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include #endif @@ -132,7 +132,7 @@ void get_bus_conf(void) m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index d9d5218bb8..2f5be994c8 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -226,7 +226,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 6a1fd7769f..fe5fcde226 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -23,7 +23,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include #endif @@ -128,7 +128,7 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 90b53357ad..d0fb54145d 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -97,7 +97,7 @@ static void h8scm_enable(device_t dev) /* get_ide_dma66(); */ } -#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +#if CONFIG_HAVE_MAINBOARD_RESOURCES int add_mainboard_resources(struct lb_memory *mem) { return 0; diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 0c75d1a15b..2e50b84950 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin)) #else diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 70b3a0470d..6ad1484462 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); -- cgit v1.2.3