From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 9ff43396ca..7ae3d70fad 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -36,7 +36,7 @@ void set_pcie_reset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); } @@ -45,7 +45,7 @@ void set_pcie_dereset(void) { struct device *pcie_core_dev; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pcie_core_dev = pcidev_on_root(0, 0); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); } -- cgit v1.2.3