From 6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 21 Nov 2010 11:36:03 +0000 Subject: Use DIMM0 et al in lots more places instead of hardocding values. The (0xa << 3) expression equals 0x50, i.e. DIMM0. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/supermicro/h8dme/romstage.c | 17 +++++++++-------- src/mainboard/supermicro/h8dmr/romstage.c | 9 +++++---- src/mainboard/supermicro/x6dai_g/romstage.c | 9 +++------ src/mainboard/supermicro/x6dhe_g/romstage.c | 5 +++-- src/mainboard/supermicro/x6dhe_g2/romstage.c | 9 +++------ src/mainboard/supermicro/x6dhr_ig/romstage.c | 5 +++-- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 9 +++------ 7 files changed, 29 insertions(+), 34 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 86705fdfb6..4f32816ebb 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -32,6 +32,7 @@ #include #include +#include #include @@ -188,15 +189,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ static const uint16_t spd_addr[] = { // Node 0 - RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2, - RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6, - RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3, - RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7, + RC0 | DIMM0, RC0 | DIMM2, + RC0 | DIMM4, RC0 | DIMM6, + RC0 | DIMM1, RC0 | DIMM3, + RC0 | DIMM5, RC0 | DIMM7, // Node 1 - RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2, - RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6, - RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3, - RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7, + RC1 | DIMM0, RC1 | DIMM2, + RC1 | DIMM4, RC1 | DIMM6, + RC1 | DIMM1, RC1 | DIMM3, + RC1 | DIMM5, RC1 | DIMM7, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index b84bdea2eb..eb5cc05c7a 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -35,6 +35,7 @@ #include #include +#include #include @@ -124,11 +125,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 6a7d77b3bd..6f3c671dc3 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -20,6 +20,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" +#include #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -44,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -55,8 +52,8 @@ static void main(unsigned long bist) .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 64196b2fc5..18d8b265b2 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -21,6 +21,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -58,8 +59,8 @@ static void main(unsigned long bist) .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, - .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, + .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, } }; diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 39cf5e778a..e8fcf306b7 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -19,6 +19,7 @@ #include "superio/nsc/pc87427/pc87427_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2) @@ -43,10 +44,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -56,8 +53,8 @@ static void main(unsigned long bist) .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 4dc5efe94a..0a9af2d3bf 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -19,6 +19,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -57,8 +58,8 @@ static void main(unsigned long bist) .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 6d8e482463..efdacb5a5a 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -19,6 +19,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -44,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -57,8 +54,8 @@ static void main(unsigned long bist) .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; -- cgit v1.2.3