From 600fa266bdc8740126420e63579a5b9d103ca960 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 08:04:59 +0100 Subject: nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree Change-Id: I955274bc6bda587201f130762c0735c36f5501d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x10slm-f/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 6cd3ab7933..959c3b81db 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell device cpu_cluster 0 on + ops haswell_cpu_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end @@ -10,6 +11,7 @@ chip northbridge/intel/haswell end device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x15d9 0x0803 inherit device pci 00.0 on end # Host bridge -- cgit v1.2.3