From 5c62375222997d62a796a521b9c8af521882dbe2 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 22 Dec 2013 23:14:27 +0200 Subject: AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Paul Menzel --- src/mainboard/supermicro/h8dme/romstage.c | 2 -- src/mainboard/supermicro/h8dmr/romstage.c | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 1505794781..48c6156572 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -205,9 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif /* dump_smbus_registers(); */ setup_coherent_ht_domain(); // routing table and start other core0 diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 2709e1d201..c97eef30bd 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -132,9 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -- cgit v1.2.3