From 52919523c14396a8a5dffa34afe40b24b7d68dfc Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 21:44:36 +0200 Subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 435015b93f..bbc52db5e7 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -8,7 +8,6 @@ chip soc/intel/skylake # FSP Configuration register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Disabled" @@ -140,6 +139,7 @@ chip soc/intel/skylake device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # SPI #0 + device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC Interface chip superio/common device pnp 2e.0 on end -- cgit v1.2.3