From 3e4f7a39f8cbdfc7cd097b5c57c43f52d9b0fb4c Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Fri, 10 Jan 2020 13:23:02 -0600 Subject: mainboard: add Supermicro X9SCL/X9SCM Boots to Linux. Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7 To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants) Signed-off-by: Jonathan A. Kollasch Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x9scl/Kconfig | 55 +++++++ src/mainboard/supermicro/x9scl/Kconfig.name | 2 + src/mainboard/supermicro/x9scl/Makefile.inc | 4 + src/mainboard/supermicro/x9scl/acpi/ec.asl | 0 src/mainboard/supermicro/x9scl/acpi/platform.asl | 11 ++ src/mainboard/supermicro/x9scl/acpi/superio.asl | 12 ++ src/mainboard/supermicro/x9scl/acpi_tables.c | 10 ++ src/mainboard/supermicro/x9scl/board_info.txt | 7 + src/mainboard/supermicro/x9scl/devicetree.cb | 127 ++++++++++++++++ src/mainboard/supermicro/x9scl/dsdt.asl | 65 ++++++++ src/mainboard/supermicro/x9scl/early_init.c | 158 +++++++++++++++++++ src/mainboard/supermicro/x9scl/gpio.c | 183 +++++++++++++++++++++++ src/mainboard/supermicro/x9scl/hda_verb.c | 9 ++ src/mainboard/supermicro/x9scl/x9scl.h | 13 ++ 14 files changed, 656 insertions(+) create mode 100644 src/mainboard/supermicro/x9scl/Kconfig create mode 100644 src/mainboard/supermicro/x9scl/Kconfig.name create mode 100644 src/mainboard/supermicro/x9scl/Makefile.inc create mode 100644 src/mainboard/supermicro/x9scl/acpi/ec.asl create mode 100644 src/mainboard/supermicro/x9scl/acpi/platform.asl create mode 100644 src/mainboard/supermicro/x9scl/acpi/superio.asl create mode 100644 src/mainboard/supermicro/x9scl/acpi_tables.c create mode 100644 src/mainboard/supermicro/x9scl/board_info.txt create mode 100644 src/mainboard/supermicro/x9scl/devicetree.cb create mode 100644 src/mainboard/supermicro/x9scl/dsdt.asl create mode 100644 src/mainboard/supermicro/x9scl/early_init.c create mode 100644 src/mainboard/supermicro/x9scl/gpio.c create mode 100644 src/mainboard/supermicro/x9scl/hda_verb.c create mode 100644 src/mainboard/supermicro/x9scl/x9scl.h (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig new file mode 100644 index 0000000000..df6308e6ba --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -0,0 +1,55 @@ +if BOARD_SUPERMICRO_X9SCL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select RAMINIT_ENABLE_ECC + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default supermicro/x9scl + +config MAINBOARD_PART_NUMBER + string + default "X9SCL/X9SCM" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config VGA_BIOS_FILE + string + default "pci102b,0532.rom" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "102b,0532" + +config PXE_ROM_ID + string + depends on PXE + default "8086:10d3" + +config CBFS_SIZE + hex + default 0x400000 + +#config SUPERMICRO_BOARDID +# string +# default "0624" +# +endif diff --git a/src/mainboard/supermicro/x9scl/Kconfig.name b/src/mainboard/supermicro/x9scl/Kconfig.name new file mode 100644 index 0000000000..e0e91f1dae --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL + bool "X9SCL/X9SCM" diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc new file mode 100644 index 0000000000..3465dfeca6 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl/acpi/ec.asl b/src/mainboard/supermicro/x9scl/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/supermicro/x9scl/acpi/platform.asl b/src/mainboard/supermicro/x9scl/acpi/platform.asl new file mode 100644 index 0000000000..4c72ad8884 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/supermicro/x9scl/acpi/superio.asl b/src/mainboard/supermicro/x9scl/acpi/superio.asl new file mode 100644 index 0000000000..0fffbe8aef --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#undef NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#undef NCT6776_SHOW_GPIO +#define NCT6776_SHOW_HWM + +#include diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c new file mode 100644 index 0000000000..3851d04b22 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl/board_info.txt b/src/mainboard/supermicro/x9scl/board_info.txt new file mode 100644 index 0000000000..a14680e826 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb new file mode 100644 index 0000000000..9236f6f3da --- /dev/null +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -0,0 +1,127 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x15d9 0x0624 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 01.1 on end # PEG + device pci 02.0 off end # iGPU + device pci 06.0 on end # PEG + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) + register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) + register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + subsystemid 0x15d9 0x1502 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + device pci 00.0 on end # primary 574 GigE + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on # PCIe Port #7 + device pci 00.0 on end # secondary 574 GigE on X9SCL+-F + end + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on # PCI bridge + device pci 03.0 on end # Matrox G200e in BMC + end + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.307 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIOBASE + io 0x60 = 0xa80 + end + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 on # GPIO2 + end + device pnp 2e.309 on # GPIO3 + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0xa30 + io 0x62 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/ipmi + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 off end # IPMI KCS + end + chip superio/nuvoton/wpcm450 + device pnp 164e.2 on + io 0x60 = 0x03e8 + irq 0x70 = 10 + end + device pnp 164e.3 off end + device pnp 164e.6 off end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl new file mode 100644 index 0000000000..b6c8930cb6 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT Revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20171231 /* OEM Revision */ +) +{ + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + Device (PCIB) + { + Name (_ADR, 0x001E0000) + Name (_PRW, Package(){ 13, 4 }) + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0003ffff, 0, 0, 0x17 }, + }) + } + Return (Package() { + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } + } + } + + Scope (\_SB.PCI0.PEGP.DEV0) + { + Name (_SUN, 7) + } + + Scope (\_SB.PCI0.PEG1.DEV0) + { + Name (_SUN, 6) + } + + Scope (\_SB.PCI0.PEG6.DEV0) + { + Name (_SUN, 5) + } + + Scope (\_SB.PCI0.RP01) + { + Device (DEV0) + { + Name (_ADR, 0x00000000) + Name (_SUN, 4) + } + } +} diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c new file mode 100644 index 0000000000..b4a39fe11f --- /dev/null +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "x9scl.h" + +#define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1) +#define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11) + +#define SUPERIO_INITVAL(reg, data) {(reg), (data)} +#define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x)) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ + { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ + { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ + { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ + { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ + { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ + { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ + { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ + { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ + { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ + { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ + { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +static const uint8_t superio_initvals[][2] = { + /* Global config registers */ + SUPERIO_INITVAL(0x1a, 0xc8), + SUPERIO_INITVAL(0x1b, 0x68), + SUPERIO_INITVAL(0x1c, 0x83), + SUPERIO_INITVAL(0x24, 0x24), + //SUPERIO_INITVAL(0x27, 0x00), + SUPERIO_INITVAL(0x2a, 0x00), + SUPERIO_INITVAL(0x2b, 0x42), + SUPERIO_INITVAL(0x2c, 0x80), + + SUPERIO_BANK(0x9), /* GPIO[2345] */ + SUPERIO_INITVAL(0x30, 0x0c), + SUPERIO_INITVAL(0xe0, 0xcf), + SUPERIO_INITVAL(0xe4, 0xbd), + SUPERIO_INITVAL(0xe5, 0x42), + SUPERIO_INITVAL(0xe9, 0x10), + SUPERIO_INITVAL(0xea, 0x40), + SUPERIO_INITVAL(0xf0, 0xff), + SUPERIO_INITVAL(0xf1, 0x02), + + SUPERIO_BANK(0xb), /* HWM & LED */ + SUPERIO_INITVAL(0xf7, 0x07), + SUPERIO_INITVAL(0xf8, 0x40), + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, X9SCL_NCT6776_HWM_BASE >> 8), + SUPERIO_INITVAL(0x61, X9SCL_NCT6776_HWM_BASE & 0xff), + + SUPERIO_BANK(0x5), /* KBC */ + SUPERIO_INITVAL(0xf0, 0x83), + SUPERIO_INITVAL(0x30, 0x01), + + SUPERIO_BANK(0x0), /* FDC */ + SUPERIO_INITVAL(0x30, 0x80), + +#if 0 + SUPERIO_BANK(8), + SUPERIO_INITVAL(0x30, 0x0a), + SUPERIO_INITVAL(0x60, X9SCL_NCT6776_GPIO_BASE >> 8), + SUPERIO_INITVAL(0x61, X9SCL_NCT6776_GPIO_BASE & 0xff), + SUPERIO_INITVAL(0xe1, 0xf9), + + SUPERIO_BANK(0xa), + SUPERIO_INITVAL(0xe4, 0x60), +#endif +}; + + +static void superio_init(void) +{ + const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0); + + nuvoton_pnp_enter_conf_state(dev); + for (size_t i = 0; i < ARRAY_SIZE(superio_initvals); i++) + pnp_write_config(dev, superio_initvals[i][0], superio_initvals[i][1]); + nuvoton_pnp_exit_conf_state(dev); +} + +static void bmc_init(void) +{ + pnp_devfn_t dev = KCS_DEV; + + pnp_write_config(dev, 0x21, 0x11); + + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, X9SCL_WPCM450_KCS_BASE + 0); + pnp_set_iobase(dev, PNP_IDX_IO1, X9SCL_WPCM450_KCS_BASE + 1); + pnp_set_iobase(dev, PNP_IDX_IRQ0, 0); + pnp_set_enable(dev, 1); + +#if 0 + //wpcm450_enable_dev(WPCM450_SP2, X9SCL_WPCM450_PNP_BASE, 0x03e8); + //wpcm450_enable_dev(WPCM450_SP1, X9SCL_WPCM450_PNP_BASE, 0x02e8); +#endif + +#if 0 + dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x03e8); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x02e8); + pnp_set_enable(dev, 0); +#endif +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + superio_init(); + bmc_init(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_early_init(int s3resume) +{ + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); +} diff --git a/src/mainboard/supermicro/x9scl/gpio.c b/src/mainboard/supermicro/x9scl/gpio.c new file mode 100644 index 0000000000..04ea4825fe --- /dev/null +++ b/src/mainboard/supermicro/x9scl/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl/hda_verb.c b/src/mainboard/supermicro/x9scl/hda_verb.c new file mode 100644 index 0000000000..57c3cff83a --- /dev/null +++ b/src/mainboard/supermicro/x9scl/hda_verb.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl/x9scl.h b/src/mainboard/supermicro/x9scl/x9scl.h new file mode 100644 index 0000000000..05723145dc --- /dev/null +++ b/src/mainboard/supermicro/x9scl/x9scl.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef X9SCL_H +#define X9SCL_H + +#define X9SCL_NCT6776_PNP_BASE 0x002e +#define X9SCL_NCT6776_HWM_BASE 0x0a30 +#define X9SCL_NCT6776_GPIO_BASE 0x0a80 +#define X9SCL_WPCM450_KCS_BASE 0x0ca2 +#define X9SCL_WPCM450_PNP_BASE 0x164e + +#endif /* X9SCL_H */ -- cgit v1.2.3