From 0caf80d8aaa383d40618343f14ed78774108053d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 4 Jun 2021 11:18:39 +0200 Subject: bd82x6x boards: Drop redundant `c2_latency` If unspecified, chipset code already uses 101, and 0x65 == 101. Change-Id: I524ca492fa577003df23017756f74a455582132f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/supermicro/x9scl/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 13b20437ab..49fcff5a6d 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge device pci 02.0 off end # iGPU device pci 06.0 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) -- cgit v1.2.3