From f8ee1806ac524bc782c93eccc59ee3c929abddb9 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 18 Jan 2008 15:08:58 +0000 Subject: Rename almost all occurences of LinuxBIOS to coreboot. Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/supermicro/x6dhr_ig2/Options.lb | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard/supermicro/x6dhr_ig2/Options.lb') diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb index d92a8fd0a3..369cbe542d 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb @@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -75,7 +75,7 @@ default CONFIG_UDELAY_TSC=1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -97,7 +97,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -125,10 +125,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -144,12 +144,12 @@ default HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072 ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -199,7 +199,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately -- cgit v1.2.3