From 5878bbd935c8cbd7c6d25ef72a5460f3262119e7 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 17 Dec 2014 02:46:24 +0100 Subject: Drop Intel E7520 and E7525 and related boards There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/mainboard/supermicro/x6dai_g/mptable.c | 88 ------------------------------ 1 file changed, 88 deletions(-) delete mode 100644 src/mainboard/supermicro/x6dai_g/mptable.c (limited to 'src/mainboard/supermicro/x6dai_g/mptable.c') diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c deleted file mode 100644 index 0efae773c7..0000000000 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ /dev/null @@ -1,88 +0,0 @@ -#include -#include -#include -#include -#include -#include - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_6300; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* southbridge */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_6300 = 5; - } - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - /* Slot 1 function 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 4, 0x04, 0x03, 0x00); - /* Slot 2 function 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 4, 0x0c, 0x03, 0x01); - /* Slot 3 function 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_6300, 0x20, 0x02, 0x14); - /* Slot 4 function 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_6300, 0x08, 0x02, 0x15); - /* On board NIC */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_6300, 0x0c, 0x02, 0x16); - - /* Standard local interrupt assignments */ -// smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, -// bus_isa, 0x00, MP_APIC_ALL, 0x00); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} -- cgit v1.2.3