From 9a1b47e8a005e87ed6be0c8d62c62e5e7007b3e3 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 23 Oct 2023 17:37:21 +0200 Subject: mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arrays In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they will be moved into the devicetree to their related root ports at some later point. While on it, remove superfluous comments related to modified lines. Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- .../variants/x11ssw-f/overridetree.cb | 58 +++++++++------------- 1 file changed, 23 insertions(+), 35 deletions(-) (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb') diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index 6984b834ed..c5c2778a20 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -15,43 +15,31 @@ chip soc/intel/skylake # This board has an IGD with no output. register "PrimaryDisplay" = "Display_Auto" - # USB configuration # NB: Overcurrent OCx values untested - # USB2/3 - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */ + [1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */ + [2] = USB2_PORT_MID(OC2), /* USB 0 */ + [3] = USB2_PORT_MID(OC2), /* USB 1 */ + [4] = USB2_PORT_MID(OC1), /* USB 4 */ + [5] = USB2_PORT_MID(OC1), /* USB 5 */ + [8] = USB2_PORT_MID(OC0), /* USB 2 */ + [9] = USB2_PORT_MID(OC0), /* USB 3 */ + [10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */ + [11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ + [12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */ + [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ + [14] = USB2_PORT_MID(OC0), /* Unknown */ + [15] = USB2_PORT_MID(OC0), /* Unknown */ + }" - # ? - register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" - - # USB4/5 - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" - - # USB0/1 - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" - - # USB6/7 (USB3.0) - register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" - - # USB8 (USB3.0) - register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" - - # USB9/10 (USB3.0) - register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" - - - # IPMI USB HUB - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */ + [1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */ + [2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */ + [3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */ + [4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ + }" device domain 0 on device pci 01.0 on -- cgit v1.2.3