From ddd44f4fe9f45dfcdb2467073b4faf1fdb03ce47 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 24 Nov 2020 01:23:28 +0100 Subject: mb/supermicro/x11-lga1151-series: restructure and clean up devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Arthur Heymans --- .../variants/x11ssh-tf/overridetree.cb | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf') diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 7996791a69..093786cbd5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -11,19 +11,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # PCIe configuration - # Enable JPCIE1 - register "PcieRpEnable[0]" = "1" - - # Enable ASpeed PCI bridge - register "PcieRpEnable[2]" = "1" - - # Enable X550T (10GbE) - register "PcieRpEnable[4]" = "1" - - # Enable M.2 - register "PcieRpEnable[8]" = "1" - # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" @@ -66,9 +53,11 @@ chip soc/intel/skylake device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) + register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device pci 1c.2 on # PCI Express Port 3 @@ -77,10 +66,12 @@ chip soc/intel/skylake end end device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device pci 1f.0 on # LPC Interface -- cgit v1.2.3