From 1295fa218fc2b02d5e143d15edb1c5c09221a508 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Sat, 27 Feb 2021 23:58:56 +0100 Subject: mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-F MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- .../x11-lga1151-series/variants/x11ssh-f/overridetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb') diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index c3f4bf1e6f..35825f8630 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -67,6 +67,14 @@ chip soc/intel/skylake register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end + device pci 1c.2 on # PCI Express Port 3 only on -LN4F + register "PcieRpEnable[2]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.3 on # PCI Express Port 4 only on -LN4F + register "PcieRpEnable[3]" = "1" + device pci 00.0 on end # GbE + end device pci 1c.4 on # PCI Express Port 5 register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" -- cgit v1.2.3