From 9a369718d668601da13030e9b57cd1a3e313cf5d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 20:36:50 +0200 Subject: haswell: Factor out `max_ddr3_freq` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All mainboards choose the maximum speed of DDR3-1600. Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120 Reviewed-by: Patrick Rudolph Reviewed-by: Tristan Corrick Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x10slm-f/romstage.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/supermicro/x10slm-f') diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index ce8f888d13..09e8df1a6f 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -29,7 +29,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[3] = 0xa6; pei_data->ec_present = 0; pei_data->ddr_refresh_2x = 1; - pei_data->max_ddr3_freq = 1600; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ -- cgit v1.2.3