From 00c8c4a31632150fa711493f39e727da950ebe9f Mon Sep 17 00:00:00 2001 From: efdesign98 Date: Wed, 20 Jul 2011 12:37:58 -0600 Subject: Update AMD SR5650 and SB700 This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She Reviewed-by: Marc Jones --- src/mainboard/supermicro/h8scm_fam10/romstage.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) mode change 100644 => 100755 src/mainboard/supermicro/h8scm_fam10/romstage.c (limited to 'src/mainboard/supermicro/h8scm_fam10/romstage.c') diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c old mode 100644 new mode 100755 index 8101d2fad2..6e6e3940df --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -42,13 +42,14 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include #include "cpu/x86/bist.h" -#include "superio/nuvoton/wpcm450/early_init.c" #include #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/sb700/early_setup.c" -#include "southbridge/amd/sr5650/early_setup.c" +#include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/smbus.h" +#include "southbridge/amd/sr5650/sr5650.h" +#include "superio/nuvoton/wpcm450/wpcm450.h" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) @@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) static int spd_read_byte(u32 device, u32 address) { - return smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } #include "northbridge/amd/amdfam10/amdfam10.h" @@ -102,7 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - disable_pcie_bridge(); + /* SR56x0 pcie bridges block pci_locate_device() before pcie training. + * disable all pcie bridges on SR56x0 to work around it + */ + sr5650_disable_pcie_bridge(); sb7xx_51xx_lpc_port80(); } @@ -181,7 +185,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ sr5650_early_setup(); - disable_pcie_bridge(); sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID -- cgit v1.2.3