From f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:55:05 +0100 Subject: mb/*/*: Drop AMDFAM10 mainboards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 80 ------------------------ 1 file changed, 80 deletions(-) delete mode 100644 src/mainboard/supermicro/h8scm_fam10/mainboard.c (limited to 'src/mainboard/supermicro/h8scm_fam10/mainboard.c') diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c deleted file mode 100644 index b16f7a24d1..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * TODO: Add the routine info of each PCIE_RESET_L. - * TODO: Add the reset of each PCIE_RESET_L. - * PCIE_RESET_GPIO1 -> Slot 0 - * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709 - * PCIE_RESET_GPIO3 -> TMS - * PCIE_RESET_GPIO4 -> Slot 1 - * PCIE_RESET_GPIO5 -> Slot 2 - ***/ -void set_pcie_reset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); -} - -void set_pcie_dereset(void) -{ - struct device *pcie_core_dev; - - pcie_core_dev = pcidev_on_root(0, 0); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); -} - -/************************************************* -* enable the dedicated function in h8scm board. -* This function called early than sr5650_enable. -*************************************************/ -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); - - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - set_pcie_dereset(); - /* get_ide_dma66(); */ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; -- cgit v1.2.3