From eef45f9cfd016343fbcf92b4df5b3d76a39c5136 Mon Sep 17 00:00:00 2001 From: Kimarie Hoot Date: Fri, 8 Mar 2013 13:54:10 -0700 Subject: Supermicro H8QGI: Use SPD read code from F15 wrapper Changes: - Get rid of the h8qgi mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - select_socket() and restore_socket() started by duplicating sp5100_set_gpio() and sp5100_restore_gpio(), which were in dimmSpd.c. In addition to renaming the functions to more specifically state their purpose, some cleanup and magic number reduction was done. Change-Id: I346ebd8399d4ba3e280576e667fdc62fa75a63b8 Signed-off-by: Kimarie Hoot Reviewed-on: http://review.coreboot.org/2828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 65 +++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 3 deletions(-) (limited to 'src/mainboard/supermicro/h8qgi/BiosCallOuts.c') diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 1499d54792..178a788214 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -23,6 +23,54 @@ #include "Ids.h" #include "OptionsIds.h" #include "heapManager.h" +#include +#include +#include + +#ifdef __PRE_RAM__ +/* These defines are used to select the appropriate socket for the SPD read + * because this is a multi-socket design. + */ +#define PCI_REG_GPIO_56_to_53_CNTRL (0x52) +#define GPIO_OUT_BIT_GPIO53 (BIT0) +#define GPIO_OUT_BIT_GPIO54 (BIT1) +#define GPIO_OUT_ENABLE_BIT_GPIO53 (BIT4) +#define GPIO_OUT_ENABLE_BIT_GPIO54 (BIT5) + +#define GPIO_OUT_BIT_GPIO54_to_53_MASK \ + (GPIO_OUT_BIT_GPIO54 | GPIO_OUT_BIT_GPIO53) +#define GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK \ + (GPIO_OUT_ENABLE_BIT_GPIO54 | GPIO_OUT_ENABLE_BIT_GPIO53) + +static UINT8 select_socket(UINT8 socket_id) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus + UINT8 value = 0; + UINT8 gpio56_to_53 = 0; + + /* Configure GPIO54,53 to select the desired socket + * GPIO54,53 control the HC4052 S1,S0 + * S1 S0 true table + * 0 0 channel 1 (Socket1) + * 0 1 channel 2 (Socket2) + * 1 0 channel 3 (Socket3) + * 1 1 channel 4 (Socket4) + */ + gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL); + value = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK); + value |= socket_id; + value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0=Output Enabled, 1=Tristate + pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value); + + return gpio56_to_53; +} + +static void restore_socket(UINT8 original_value) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus + pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, original_value); +} +#endif STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -81,8 +129,6 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = }, }; -extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); - AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { UINTN i; @@ -487,7 +533,20 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); +#ifdef __PRE_RAM__ + UINT8 original_value = 0; + + if (ConfigPtr == NULL) + return AGESA_ERROR; + + original_value = select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId); + + Status = agesa_ReadSPD (Func, Data, ConfigPtr); + + restore_socket(original_value); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } -- cgit v1.2.3