From fb2f667da2091ce2194274f95c2d5db024d46e63 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 Mar 2017 11:50:10 +0200 Subject: nb/amd/amdk8: Link raminit_f.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For this debug.c needs to be linked too. Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/sunw/ultra40/romstage.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/sunw/ultra40') diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index a1659b7f84..7df486a438 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -15,7 +15,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include "superio/smsc/lpc47b397/early_gpio.c" @@ -26,7 +26,7 @@ #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400 -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) @@ -40,9 +40,9 @@ static void sio_gpio_setup(void) } #endif -static inline void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -- cgit v1.2.3