From d4b278c02c1da92219ebeb34204b9768934aeca3 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Wed, 4 Oct 2006 20:46:15 +0000 Subject: AMD Rev F support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/sunw/ultra40/Options.lb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/sunw/ultra40') diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb index 32748f5f1d..a81745390d 100644 --- a/src/mainboard/sunw/ultra40/Options.lb +++ b/src/mainboard/sunw/ultra40/Options.lb @@ -52,7 +52,7 @@ uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_HW_MEM_HOLE_SIZEK +uses HW_MEM_HOLE_SIZEK uses K8_HT_FREQ_1G_SUPPORT uses USE_DCACHE_RAM @@ -66,7 +66,7 @@ uses LIFT_BSP_APIC_ID uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE -uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY ## ROM_SIZE is the size of boot ROM that this board will use. @@ -134,7 +134,7 @@ default CONFIG_LOGICAL_CPUS=1 #default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_HW_MEM_HOLE_SIZEK=0x100000 +default HW_MEM_HOLE_SIZEK=0x100000 #Opteron K8 1G HT Support default K8_HT_FREQ_1G_SUPPORT=1 @@ -146,7 +146,7 @@ default HT_CHAIN_UNITID_BASE=0x0 #default HT_CHAIN_END_UNITID_BASE=0x0 #make the SB HT chain on bus 0, default is not (0) -default K8_SB_HT_CHAIN_ON_BUS0=2 +default SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 -- cgit v1.2.3