From 7f66fa4299ff5f64c94093a2a19b688dd5e80078 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 12 Aug 2024 10:04:22 +0100 Subject: mb/starlabs/starlite_adl: Alphabetize and group FSP UPDs Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881 Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- .../starlabs/starlite_adl/variants/mk_v/devicetree.cb | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'src/mainboard/starlabs/starlite_adl') diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index a302e4f1c4..fc21f18d74 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -8,13 +8,11 @@ chip soc/intel/alderlake }, }" - # FSP Memory - register "sagv" = "SaGv_Enabled" - - # FSP Silicon - register "eist_enable" = "true" - register "cnvi_bt_core" = "true" + # FSP UPDs register "cnvi_bt_audio_offload" = "true" + register "cnvi_bt_core" = "true" + register "eist_enable" = "true" + register "sagv" = "SaGv_Enabled" # Serial I/O register "serial_io_i2c_mode" = "{ -- cgit v1.2.3