From fe2f50f49669dead4e39a16a50fac9d5f1465078 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 2 Feb 2023 15:53:03 +0000 Subject: mb/starlabs/starbook/adl: Enable ASPM Enable ASPM for RP5 (wireless) and RP9 (SSD). Signed-off-by: Sean Rhodes Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/starlabs/starbook') diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 4b833ffa60..c43f6a6eba 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -100,6 +100,8 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" @@ -117,6 +119,9 @@ chip soc/intel/alderlake .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthLong" -- cgit v1.2.3