From 076f86125f5578b0cc58fa219f80a5a39af31b99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 7 Apr 2023 17:05:49 +0000 Subject: Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/starlabs/starbook/variants') diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index c3a3f45546..cd8c48071a 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -19,6 +19,7 @@ chip soc/intel/tigerlake register "CnviBtAudioOffload" = "1" register "enable_c6dram" = "1" register "SaGv" = "SaGv_Enabled" + register "TcssD3ColdDisable" = "1" # FSP Silicon # Serial I/O -- cgit v1.2.3