From 2e1aa62839038339cdeee174d2fb2711fe5d9152 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 9 Sep 2024 12:56:31 +0100 Subject: mb/starlabs/starbook/kbl: Alphabetize and group FSP UPDs Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/mainboard/starlabs/starbook/variants/kbl') diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 87ccb8a035..bc8bc62c23 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake -# CPU - # Enable Enhanced Intel SpeedStep + # FPD UPDs register "eist_enable" = "true" + register "SaGv" = "SaGv_Enabled" # Graphics # IGD Displays @@ -14,10 +14,6 @@ chip soc/intel/skylake .backlight_pwm_hz = 200, // PWM }" - # FSP Memory - register "SaGv" = "SaGv_Enabled" - -# FSP Silicon # Serial I/O register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- cgit v1.2.3