From 68f33d228ef2a79878042b7d62db63f73fa77561 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 3 Oct 2024 11:12:54 +0100 Subject: mb/starlabs/*: Enhance USB configuration and comments Some boards use hubs for devices, so correct the ACPI configuration for these ports. Also, add more information to the comments for the ports. Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/starlabs/lite/variants/glkr/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/starlabs/lite/variants/glkr') diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index bfe9d51a5a..4c79364592 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -76,15 +76,15 @@ chip soc/intel/apollolake register "sata_ports_enable[0]" = "1" end device ref xhci on - # Motherboard USB Type C + # Motherboard USB 3.0 Type-C register "usb2_port[0]" = "PORT_EN(OC1)" register "usb3_port[0]" = "PORT_EN(OC1)" - # Motherboard USB 3.0 + # Motherboard USB 3.0 Type-A register "usb2_port[1]" = "PORT_EN(OC0)" register "usb3_port[1]" = "PORT_EN(OC0)" - # Daughterboard USB 3.0 + # Daughterboard USB 3.0 Type-A register "usb2_port[3]" = "PORT_EN(OC1)" register "usb3_port[4]" = "PORT_EN(OC1)" -- cgit v1.2.3