From 9ca43191ab454c777102f9634b5d40478cd4dc58 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 29 Jan 2019 08:54:52 +0100 Subject: siemens/mc_apl2: Change SERIRQ mode Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used. The problem is described in Intel document 334820-007 under point APL47. Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/31138 Reviewed-by: Angel Pons Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/siemens') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index e54444ac65..c362e6c0a9 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -5,7 +5,6 @@ chip soc/intel/apollolake end register "sci_irq" = "SCIS_IRQ10" - register "serirq_mode" = "SERIRQ_CONTINUOUS" # Disable all clkreq of PCIe root ports as SMARC interface do not # have this pins. -- cgit v1.2.3