From 89c497b6d1aaaf0de399977279940d7c2bc00769 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 28 Apr 2022 14:48:23 +0200 Subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/siemens') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index 0dfd2d8a5a..36252a79a3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -9,9 +10,16 @@ void variant_mainboard_final(void) { + struct device *dev; + /* PIR8 register mapping for PCIe root ports INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ pcr_write16(PID_ITSS, 0x3150, 0x1032); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); } static void finalize_boot(void *unused) -- cgit v1.2.3