From 4f7fe494a009a6edc37a5e897de5f5ae32fbb055 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 8 Nov 2019 09:50:20 +0100 Subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge On this mainboard variant the PCIe-2-PCI bridge is used a bit different. Adjust the switched off clock lines to match the mainboard configuration. Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/siemens') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 6a883c6a26..f908ab6713 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -60,12 +60,12 @@ void variant_mainboard_final(void) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); - /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + /* Disable clock outputs 0-3 (CLKOUT) for upstream * XIO2001 PCIe to PCI Bridge. */ struct device *parent = dev->bus->dev; if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) - pci_write_config8(parent, 0xd8, 0x1d); + pci_write_config8(parent, 0xd8, 0x0F); } /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI -- cgit v1.2.3