From f61070e87c80e75793f755a544f6f2f5465a9cc8 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 21 Oct 2022 11:53:19 +0200 Subject: mb/siemens/mc_ehl1: Disable L1 prefetcher The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/siemens/mc_ehl') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index bc3c4a0e06..319a843722 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -132,6 +132,9 @@ chip soc/intel/elkhartlake .vcc_low_high_us = 50, }" + # Disable L1 prefetcher + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3