From ce6cdb360810938ab5800cb2d9f4f3c6e4d9fad8 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 22 Dec 2022 11:09:34 +0100 Subject: mb/siemens/mc_ehl1: Limit SATA speed to Gen 2 Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Arthur Heymans --- src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/siemens/mc_ehl') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 319a843722..82070785fc 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -82,6 +82,7 @@ chip soc/intel/elkhartlake register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" + register "SataSpeed" = "SATA_GEN2" register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" -- cgit v1.2.3