From 0853055ef7642ef1bff6beeb8a3f3348343e4d44 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 14 Mar 2017 14:27:29 +0100 Subject: siemens/mc_apl1: Clean up the code This patch make some general adaptations in relation to commit 6a489237 (mainboard/intel/leafhill: Clean up). - add necessary defaults to Kconfig - remove irrelevant entries from FMD file - include romstage file for better understanding Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/18808 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_apl1/Kconfig | 4 +++ src/mainboard/siemens/mc_apl1/Makefile.inc | 5 ++++ src/mainboard/siemens/mc_apl1/mc_apl1.fmd | 44 ++++++------------------------ 3 files changed, 18 insertions(+), 35 deletions(-) (limited to 'src/mainboard/siemens/mc_apl1') diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index ef9d0216ca..83500f2906 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -16,4 +16,8 @@ config MAINBOARD_PART_NUMBER string default "MC APL1" +config MAX_CPUS + int + default 4 + endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/Makefile.inc index 9e3e892f66..b4ab8a403c 100644 --- a/src/mainboard/siemens/mc_apl1/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/Makefile.inc @@ -1,3 +1,8 @@ bootblock-y += bootblock.c +# The inclusion of romstage.c is not necessary here. +# It is put down only to the better understanding. +# The file is already included over src/arch/x86/Makefile.inc. +romstage-y += romstage.c + ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 432e8de284..8c6dda8496 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,40 +1,14 @@ FLASH 16M { - WP_RO@0x0 0xe00000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x23f000 - RO_VPD@0x240000 0x4000 - RO_SECTION@0x244000 0xbbc000 { - FMAP@0x0 0x800 - RO_UNUSED_1@0x800 0x800 - COREBOOT(CBFS)@0x1000 0xbb9000 - RO_UNUSED_2@0xbba000 0x1000 - } + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x2ff000 + FMAP@0x300000 0x800 + COREBOOT(CBFS)@0x300800 0xb9d800 + UNIFIED_MRC_CACHE@0xe9e000 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 } - MISC_RW@0xe00000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 - } - BIOS_UNUSABLE@0xe30000 0xcf000 + BIOS_UNUSABLE@0xebf000 0x40000 DEVICE_EXTENSION@0xeff000 0x100000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 UNUSED_HOLE@0xfff000 0x1000 } -- cgit v1.2.3