From ec1c0f53374effbab967cdb373f92e04a05e4443 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Mon, 21 Dec 2020 17:09:08 +0100 Subject: mb/siemens/mc_apl1: do LPC/eSPI pad configuration at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do LPC/eSPI pad configuration at board-level to match other platforms. Early gpio configuration was done in romstage, while LPC pads were configured in bootblock. Instead of adding another dedicated gpio table for bootblock, move early gpio configuration completely to bootblock on these boards. This won't hurt, since there is no code touching the pads in between. The soc code gets dropped in CB:49410. Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3 Tested-by: Mario Scheithauer Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer --- src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl2') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc index a6b80e0832..152b46ece1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += gpio.c +bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c -- cgit v1.2.3