From d958300590023fe5aedbe1cfae6ea0f62b2e207f Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Mon, 23 Oct 2017 16:10:04 +0200 Subject: siemens/mc_apl1: Add legacy IRQ routing for PCI devices On this mainboard there are PCI devices, which are connected to the PCIe root port via a PCIe-2-PCI bridge. One of the devices only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 4 (Device 14.0). The following routing is required: INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA# Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/22139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/mainboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/siemens/mc_apl1/mainboard.c') diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index f77ef75d3e..60a62a7874 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -21,7 +21,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -142,6 +144,12 @@ static void mainboard_final(void *chip_info) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); } static void wait_for_legacy_dev(void *unused) -- cgit v1.2.3