From e6063fee5c954d5acd80fd51e11aeac31e83d13d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 30 Apr 2012 14:57:51 -0700 Subject: Fix Sandybridge/Ivybridge mainboards according to code review This fixes a few cosmetics with the following three boards: - Intel Emerald Lake 2 - Samsung ChromeBook - Samsung ChromeBox The following issues were fixed: - rely on include path in ASL code instead of specifying relative paths - use updated ALIGN_CURRENT in acpi_tables.c - use preprocessor defines instead of hard coded values where possible Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563 Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/963 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/mainboard/samsung/lumpy/romstage.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src/mainboard/samsung/lumpy/romstage.c') diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 7aa4746948..82856f6b04 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -151,17 +151,17 @@ void main(unsigned long bist) #endif struct pei_data pei_data = { - .mchbar = 0xfed10000, - .dmibar = 0xfed18000, - .epbar = 0xfed19000, - .pciexbar = 0xf0000000, - .smbusbar = 0x400, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = 0xfed00000, - .rcba = 0xfed1c000, - .pmbase = 0x500, - .gpiobase = 0x480, + .hpet_address = HPET_ADDR, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, -- cgit v1.2.3