From 9ed0df4c380dc56a81a59a104b1ccac19cd52c35 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Sat, 12 Oct 2019 14:18:18 +0200
Subject: sb/intel/i82801ix: Add common code to set up LPC IO decode ranges

This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/mainboard/roda/rk9/devicetree.cb |  2 ++
 src/mainboard/roda/rk9/romstage.c    | 19 -------------------
 2 files changed, 2 insertions(+), 19 deletions(-)

(limited to 'src/mainboard/roda')

diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index 4300171207..ddb2ad72a9 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -67,6 +67,8 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }"
 
+			register "gen1_dec" = "0x000c0601"
+
 			device pci 19.0 off end # LAN
 			device pci 1a.0 on # UHCI
 				ioapic_irq 2 INTA 0x10
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 497828b58a..b37b5c5f63 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -16,27 +16,11 @@
 
 #include <arch/io.h>
 #include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <superio/smsc/lpc47n227/lpc47n227.h>
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
 
-void mb_setup_lpc(void)
-{
-	/* Set up SuperIO LPC forwards */
-
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	/* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
-}
-
 void mb_setup_superio(void)
 {
 	/* Original settings:
@@ -71,9 +55,6 @@ void mb_setup_superio(void)
 	/* Exit configuration state. */
 	pnp_exit_conf_state(sio);
 
-	/* Enable decoding of 0x600-0x60f through lpc. */
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
-
 	/* Set GPIO output values: */
 	outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
 	outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
-- 
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