From 691d58f9996d2ff3820b2c08646e98f16bbde2ee Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 11 Aug 2021 13:42:40 +0200 Subject: nb/intel/sandybridge: Add a chipset devicetree This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/roda/rv11/variants/rv11/devicetree.cb | 1 - src/mainboard/roda/rv11/variants/rw11/devicetree.cb | 1 - 2 files changed, 2 deletions(-) (limited to 'src/mainboard/roda') diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 6cb77e3aab..7cb6812695 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) register "acpi_c3" = "0" end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 2291f6141e..96a8ce848c 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) register "acpi_c3" = "0" end -- cgit v1.2.3