From 2fb6f68ef09358aa6f2550519e71a1d74702d5ef Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 09:45:19 +0100 Subject: nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/roda/rk9/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/roda') diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index c9c1896016..d4b4aef69a 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/gm45 # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end @@ -21,6 +22,7 @@ chip northbridge/intel/gm45 register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops subsystemid 0x4352 0x8986 device pci 00.0 on end # host bridge device pci 02.0 on end # VGA -- cgit v1.2.3