From af4bd5633debc8838b563c3fadd96e2b4b060ab5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 28 Dec 2021 13:05:56 +0100 Subject: sb/intel: Use `bool` for PCIe coalescing option Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/roda/rv11/variants/rv11/devicetree.cb | 2 +- src/mainboard/roda/rv11/variants/rw11/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/roda/rv11') diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 8ba2697475..6cb77e3aab 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -46,7 +46,7 @@ chip northbridge/intel/sandybridge register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 7e5555b181..2291f6141e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -51,7 +51,7 @@ chip northbridge/intel/sandybridge register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" -- cgit v1.2.3