From 0a19b080ef03ba50d111bd966c45ca90cf1507d6 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Oct 2017 15:14:38 -0600 Subject: Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/rca/rm4100/spd_table.h | 36 ------------------------------------ 1 file changed, 36 deletions(-) delete mode 100644 src/mainboard/rca/rm4100/spd_table.h (limited to 'src/mainboard/rca/rm4100/spd_table.h') diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h deleted file mode 100644 index 14bc85b724..0000000000 --- a/src/mainboard/rca/rm4100/spd_table.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -struct spd_entry { - unsigned int address; - unsigned int data; -}; - -/* - * The onboard 128MB PC133 memory does not have an SPD EEPROM so the values - * have to be set manually, the onboard memory is located in socket1 (0x51). - */ -const struct spd_entry spd_table [] = { - {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ - {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ - {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ - {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ - {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ - {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ - {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */ -}; -- cgit v1.2.3