From ffe90c528b0487ce47a123ae905be8823c5615ae Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 25 Jul 2020 08:40:15 +0200 Subject: soc/intel/skylake: Enable SMBus depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently SMBus gets enabled by the option SmbusEnable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SMBus controller. I checked all corresponding mainboards if the devicetree configuration matches the SmbusEnable setting. Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/razer') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8a369b79b9..7e96fe269e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -37,7 +37,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" -- cgit v1.2.3