From 63a078e66d3ecb9a8e23c914b5ee6d9e89ef4cf3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 16:55:04 +0100 Subject: soc/intel/skylake: Drop unreferenced PttSwitch dt setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value for this setting is not used anywhere. Drop it. Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Furquan Shaikh --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/razer') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 15ea78538e..8f3e0d6bc3 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -33,7 +33,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" -- cgit v1.2.3