From 4b7220398923af42fa39a7fcb532daf797510f77 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 20:32:15 +0200 Subject: skl mainboards/dt: Move serirq setting into LPC device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall Reviewed-by: Marvin Evers Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Erik van den Bogaert Reviewed-by: Michael Niewöhner --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/razer/blade_stealth_kbl/devicetree.cb') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 438d323b50..b8ebb1bf57 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -28,8 +28,6 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -172,6 +170,8 @@ chip soc/intel/skylake device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" -- cgit v1.2.3