From e21866781f73dfa468ce5da3db7e86b39e2bb4d8 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 23:20:52 +0200 Subject: soc/intel/skylake: Enable CIO depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/purism/librem_skl') diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 60f69c8110..23c57120f1 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -55,7 +55,6 @@ chip soc/intel/skylake register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" - register "Cio2Enable" = "0" register "ScsEmmcHs400Enabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" @@ -173,6 +172,7 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R -- cgit v1.2.3