From 5086ccef19a21bb836c6c11bb3f4fb8f993d3bc2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 1 May 2020 12:48:54 -0500 Subject: mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per the schematics, SRCCLKREQ2# is used for the NVMe and should be enabled. Enable CLKREQ for PCIe RP9, and adjust comments to indicate correct value used per schematic. Test: build/boot Librem 15v3 with NVMe drive, verify drive identified properly and no errors in boot log. Signed-off-by: Matt DeVillier Change-Id: I159cb7ce1f5195d95c0229490c3bbde26edbd375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40950 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/purism/librem_skl') diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index d273462c97..ceeeb431a7 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -167,8 +167,8 @@ chip soc/intel/skylake register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" # Enable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "0" - # ClkReq for NVMe - Bruteforced (no other value works) + register "PcieRpClkReqSupport[8]" = "1" + # SRCCLKREQ2# for NVMe per schematic register "PcieRpClkReqNumber[8]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port -- cgit v1.2.3