From 0601f1e164a95342a7c381603284c11a9a588804 Mon Sep 17 00:00:00 2001 From: Youness Alaoui Date: Fri, 9 Feb 2018 18:44:45 -0500 Subject: purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree Although VmxEnable is currently ignored by FSP, a forthcoming patch explicitly enables it in coreboot, so set it in anticipation of that. Enable Intel SpeedStep to ensure the ACPI tables are generated for the C-states/P-states which are required for the xen-acpi-processor module to be loaded. Without it, the Qubes 4.0-rc4 installer will complain at boot about modules that could not be loaded. Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387 Signed-off-by: Youness Alaoui Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/23684 Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/purism/librem_skl/variants/librem15v3') diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index d240f023da..989c4ff485 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/skylake register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + register "eist_enable" = "1" + register "VmxEnable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE -- cgit v1.2.3