From 3d80d14cd4ed82e74057cea884dcb9bb7588c076 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 12 Jan 2024 16:22:19 +0100 Subject: soc/intel/jasperlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber Signed-off-by: Nicholas Sudsgaard Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Reviewed-by: Jonathon Hall Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_jsl/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/purism/librem_jsl') diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index e3b3be2022..c992c4f2bc 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -159,7 +159,6 @@ chip soc/intel/jasperlake device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 on # PCI Express Root Port 3 - M.2 M-key, PCIe only - register "PcieRpEnable[2]" = "true" register "PcieClkSrcUsage[0]" = "2" register "PcieClkSrcClkReq[0]" = "0" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X" -- cgit v1.2.3