From 77c86aafeb56b87ee78c29b259ef8e20fbc588bc Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 15 Jun 2022 15:31:24 -0500 Subject: mb/purism/librem_cnl: convert to using overridetrees Convert the librem_14 and librem_mini from using separate devicetrees to using a baseboard devicetree and overridetrees. This reduces code duplication, and facilitates adding any new variants with minimal additional code. Test: build/boot Librem 14 and Librem Mini v2 boards Change-Id: Ide65ffc750495c9ba2074757ce467efa2f384c56 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/65187 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../librem_cnl/variants/librem_14/devicetree.cb | 283 --------------------- .../librem_cnl/variants/librem_14/overridetree.cb | 198 ++++++++++++++ .../librem_cnl/variants/librem_mini/devicetree.cb | 238 ----------------- .../variants/librem_mini/overridetree.cb | 154 +++++++++++ 4 files changed, 352 insertions(+), 521 deletions(-) delete mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb delete mode 100644 src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb create mode 100644 src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb (limited to 'src/mainboard/purism/librem_cnl/variants') diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb deleted file mode 100644 index 8b5c9086b9..0000000000 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb +++ /dev/null @@ -1,283 +0,0 @@ -chip soc/intel/cannonlake - # Lock Down - register "common_soc_config" = "{ - /* Touchpad */ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 80, - .fall_time_ns = 110, - }, - }" - -# CPU (soc/intel/cannonlake/cpu.c) - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 20, - }" - - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - -# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" - -# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - }" - - # Acoustic Noise - register "AcousticNoiseMitigation" = "1" - - register "FastPkgCRampDisableIa" = "1" - register "FastPkgCRampDisableGt" = "1" - register "FastPkgCRampDisableSa" = "1" - register "FastPkgCRampDisableFivr" = "1" - - register "SlowSlewRateForIa" = "3" # fast/16 - register "SlowSlewRateForGt" = "3" # fast/16 - register "SlowSlewRateForSa" = "3" # fast/16 - register "SlowSlewRateForFivr" = "3" # fast/16 - - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s - - # Thermal - register "tcc_offset" = "10" - -# PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" - -# Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on # Integrated Graphics Device - register "gfx" = "GMA_DEFAULT_PANEL(0)" - register "panel_cfg" = "{ - .up_delay_ms = 200, - .down_delay_ms = 50, - .cycle_delay_ms = 500, - .backlight_pwm_hz = 1000, - .backlight_on_delay_ms = 1, - .backlight_off_delay_ms = 1, - }" - end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end - device pci 12.0 on end # Thermal Subsystem - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - device usb 2.3 off end - end - chip drivers/usb/acpi - device usb 2.4 off end - end - chip drivers/usb/acpi - device usb 2.5 off end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.8 on end - end - chip drivers/usb/acpi - device usb 2.9 off end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.2 off end - end - chip drivers/usb/acpi - device usb 3.3 off end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""Card Reader"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A right - register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Webcam - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # Type-A left - register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC2)" # Type-C right - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC2)" # Type-C left - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A right - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A left - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-C right - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader - end - device pci 14.1 off end # USB xDCI (OTG) - device pci 15.0 on # I2C #0 - chip drivers/i2c/hid - register "generic.hid" = ""HTIX5288"" - register "generic.name" = ""TPD0"" - register "generic.uid" = "1" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA - register "satapwroptimize" = "1" - register "SataSalpSupport" = "1" - # Port 2 (M.2 / inner) - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - # Port 3 (M.2 / outer) - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" - end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN) - register "PcieRpEnable[6]" = "1" - register "PcieRpSlotImplemented[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - register "PcieRpHotPlug[6]" = "1" - register "PcieClkSrcUsage[2]" = "6" - register "PcieClkSrcClkReq[2]" = "2" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" - end - device pci 1c.7 on # PCI Express Port 8 - device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[3]" = "7" - register "PcieClkSrcClkReq[3]" = "3" - end - device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[8]" = "1" - register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "8" - register "PcieClkSrcClkReq[0]" = "0" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" - end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[1]" = "12" - register "PcieClkSrcClkReq[1]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" - end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Bridge - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) - register "gen1_dec" = "0x00040069" - # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen2_dec" = "0x00fc0e01" - # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen3_dec" = "0x00fc0f01" - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end - device pci 1f.1 off end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA - register "PchHdaAudioLinkHda" = "1" - end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb new file mode 100644 index 0000000000..b979740f8d --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -0,0 +1,198 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + /* Touchpad */ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 20, + }" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + }" + +# Actual device tree + device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_pwm_hz = 1000, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + }" + end + device pci 14.0 on # USB xHCI + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.2 on end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + device usb 2.4 off end + end + chip drivers/usb/acpi + device usb 2.5 off end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.8 on end + end + chip drivers/usb/acpi + device usb 2.9 off end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.2 off end + end + chip drivers/usb/acpi + device usb 3.3 off end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Card Reader"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.5 on end + end + end + end + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A right + register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Webcam + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # Type-A left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC2)" # Type-C right + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC2)" # Type-C left + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A left + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-C right + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""HTIX5288"" + register "generic.name" = ""TPD0"" + register "generic.uid" = "1" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 17.0 on # SATA + register "satapwroptimize" = "1" + register "SataSalpSupport" = "1" + # Port 2 (M.2 / inner) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 3 (M.2 / outer) + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN) + register "PcieRpEnable[6]" = "1" + register "PcieRpSlotImplemented[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpHotPlug[6]" = "1" + register "PcieClkSrcUsage[2]" = "6" + register "PcieClkSrcClkReq[2]" = "2" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" + end + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 (LAN) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe) + register "PcieRpEnable[8]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcClkReq[0]" = "0" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Bridge + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) + register "gen1_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen2_dec" = "0x00fc0e01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen3_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end +end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb deleted file mode 100644 index 08d152c574..0000000000 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ /dev/null @@ -1,238 +0,0 @@ -chip soc/intel/cannonlake - -# CPU (soc/intel/cannonlake/cpu.c) - # Power limit - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 28, - }" - - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - -# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_FixedHigh" - -# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - - # Misc - register "AcousticNoiseMitigation" = "1" - - register "FastPkgCRampDisableIa" = "1" - register "FastPkgCRampDisableGt" = "1" - register "FastPkgCRampDisableSa" = "1" - register "FastPkgCRampDisableFivr" = "1" - - register "SlowSlewRateForIa" = "3" # fast/16 - register "SlowSlewRateForGt" = "3" # fast/16 - register "SlowSlewRateForSa" = "3" # fast/16 - register "SlowSlewRateForFivr" = "3" # fast/16 - - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s - - # Thermal - register "tcc_offset" = "12" - - # Serial IRQ Mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - -# PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" - -# Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end - device pci 12.0 on end # Thermal Subsystem - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left Upper"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left Lower"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Upper"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right Lower"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right Upper"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 3)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - device usb 2.7 off end - end - chip drivers/usb/acpi - device usb 2.8 off end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Lower"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left Upper"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left Lower"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - device usb 3.2 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Lower"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Upper"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.5 on end - end - end - end - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper - end - device pci 14.1 off end # USB xDCI (OTG) - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - register "satapwroptimize" = "1" - end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) - register "PcieRpSlotImplemented[7]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC - register "PcieClkSrcUsage[2]" = "0x80" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" - end - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 - device pci 00.0 on end # x1 (LAN) - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[3]" = "9" - register "PcieClkSrcClkReq[3]" = "3" - end - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) - register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[1]" = "12" - register "PcieClkSrcClkReq[1]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" - end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC Bridge - device pci 1f.1 off end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA - register "PchHdaAudioLinkHda" = "1" - end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb new file mode 100644 index 0000000000..927031373e --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -0,0 +1,154 @@ +chip soc/intel/cannonlake + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 28, + }" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_FixedHigh" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + +# Actual device tree + device domain 0 on + device pci 14.0 on # USB xHCI + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.5 on end + end + end + end + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper + end + device pci 17.0 on # SATA + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "satapwroptimize" = "1" + end + device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC + register "PcieClkSrcUsage[2]" = "0x80" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" + end + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN) + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[3]" = "9" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) + register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + end +end -- cgit v1.2.3