From 0e4f37f7a7c7812bf15b83fd841f22b497c41e9c Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 5 Nov 2020 11:34:50 -0600 Subject: mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add strings for M.2 keying and number of PCIe lanes. Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251 Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/purism/librem_cnl/variants') diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index becb9468c7..e2135b7fa9 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -197,7 +197,7 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 -- cgit v1.2.3