From 54e0fd21b1f916a3f152114027db1029a921fc55 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 29 Oct 2020 20:30:08 -0500 Subject: mb/purism/librem_whl: rename to librem_cnl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake, rename the baseboard so that boards using other 'cannonlake family' SoCs (e.g., Cometlake) can be added with minimal confusion. Rename the mainboard dir and baseboard name, and adjust any references to them. Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/purism/librem_cnl/Makefile.inc | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 src/mainboard/purism/librem_cnl/Makefile.inc (limited to 'src/mainboard/purism/librem_cnl/Makefile.inc') diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc new file mode 100644 index 0000000000..ba157dfd05 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include -- cgit v1.2.3