From 819005332b37a424cbeeb7cc75fc9a154b55fcfb Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 30 Apr 2020 16:12:05 -0500 Subject: mb/purism/librem_bdw: Convert to use override devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40915 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons --- .../purism/librem_bdw/variants/librem15v2/overridetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb (limited to 'src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb') diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb new file mode 100644 index 0000000000..c0c8d0360f --- /dev/null +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -0,0 +1,14 @@ +chip soc/intel/broadwell + + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device domain 0 on + device pci 1d.0 on end # USB2 EHCI + end +end -- cgit v1.2.3